ERIC5 is a super-small soft-core-CPU for implementation in FPGAs. It is available for the current ALTERA, XILINX, Lattice and Actel FPGA-families. The smallest configuration takes about 110 logic-elements in a ALTERA Cyclone-family-device and operates at above 60MHz (slowest speed-grade). It is targeted for small control-applications and can replace external 8051, PICs or AVRs in many cases.

Main features:

  • small size, therefore its implementation is virtually free (in terms of required FPGA-resources) in most FPGA-designs
  • C-compiler included
  • vendor-independent, you can move your design to another architecture and reuse your CPU and software (no "sticky" IP that ties you to a specific FPGA-vendor)
  • large program-space (up to 512kB)
  • 9bit architecture to make best use of the embedded memory-blocks
  • 512byte data-space
  • optinal multiplier-support
  • easy assembler-language
  • low-cost licensing, no per-unit license-fee
  • well proven: many thousand ERICs are doing their job all over the world
ERIC5 Core User Guide: Login required.
ecc (C-Compiler) User Guide: Login required.
ericas (Assembler) User Guide: Login required
Peripherals: Login required.


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